A low-power design technique for GNSS anti-jam processor

This paper presents a low-power anti-jamming processor for Global Navigation Satellite System (GNSS) smart antenna. By improving the design of mixer in GNSS anti-interference architecture, the digital high intermediate frequency mixer and filter are optimized. To further reduce the power consumption and resource occupation, an Output Double-Rate-Register(ODDR) scheme is introduced to realize the direct synthesis of high intermediate frequency signal. The experimental results show that the power consumption and hardware resources of this design are reduced by 11％ and 14％, which can be applied to GNSS smart antenna system.