Design and implementation of closed tracking loop of navigation receiver based on SoC

The traditional satellite navigation receiver is based on FPGA+DSP architecture. Under this architecture, the tracking module is in an open-loop processing mode. It has the problems of poor real-time performance and poor reliability. At the same time, a large amount of data communication between FPGA and DSP has led to an increase in IO resources and power consumption. Based on the SoC architecture, a closed-loop tracking loop scheme for satellite navigation receiver is proposed in this paper. The entire tracking process is processed in a closed loop within the FPGA. This effectively solves the problems of open-loop tracking, and greatly reduces the amount of data communication between FPGA and CPU. In addition, all tracking channels share a tracking loop processing module through time division multiplexing, which effectively saves hardware resources and reduces costs. This paper lays a foundation for the design and development of miniaturized, low-power navigation chips.